An isolated synchronous rectifying DC/DC converter is utilized for various power source circuits including an AC/DC converter. As a kind of isolated synchronous rectifying DC/DC converter, an LLC converter is used.
FIG. 5 is a circuit diagram illustrating an example of a partial configuration of a secondary side of an LLC converter. A secondary winding W200 illustrated in FIG. 5 is included in a transformer Tr. A primary side (not shown) of the LLC converter includes a primary winding of the transformer Tr, a switching transistor, a primary side controller that drives the switching transistor, and the like.
One end of the secondary winding W200 is connected to an output terminal P200, and the other end of the secondary winding W200 is connected to a drain of a synchronous rectification transistor M200. A source of the synchronous rectification transistor M200 is connected to a ground application terminal. An output capacitor C200 is connected between the output terminal P200 and a ground.
The LLC converter has a synchronous rectification controller 300S on the secondary side. The synchronous rectification controller 300S has a gate terminal Tg1, a drain terminal Td1, a source terminal Tg2, and a drain terminal Td2 as external terminals. A gate of the synchronous rectification transistor M200 is connected to the gate terminal Tg1. The drain of the synchronous rectification transistor M200 is connected to the drain terminal Td1. The gate terminal Tg2 and the drain terminal Td2 are respectively connected to a gate and a drain of another synchronous rectification transistor (not shown) which may be provided in addition to the synchronous rectification transistor M200 on the secondary side.
The synchronous rectification controller 300S outputs a gate signal SG2 from the gate terminal Tg1 based on a drain voltage VDS2 generated at the drain terminal Td1, and controls switching of the synchronous rectification transistor M200. By the switching of the switching transistor on the primary side and the switching of the synchronous rectification transistor M200 on the secondary side, an input voltage applied to the primary winding is converted into an output voltage and output from the output terminal P200.
FIG. 7 is a timing chart illustrating a switching control of the synchronous rectification transistor M200 in the circuit illustrated in FIG. 5. In FIG. 7, a current IS2 flowing through the synchronous rectification transistor M200, the drain voltage VDS2, and the gate signal SG2 are shown sequentially from the top side.
When the switching transistor on the primary side is switched at timing t10 of FIG. 7 where the synchronous rectification transistor M200 is in an OFF state, the drain voltage VDS2 drops from a positive voltage to a negative voltage. Accordingly, the current IS2 starts to flow through a body diode BD of the synchronous rectification transistor M200. The current IS2 is a resonance current and has a sinusoidal form.
When the synchronous rectification controller 300S detects that the drain voltage VDS2 has become a negative voltage as described above, the synchronous rectification controller 300S sets the gate signal SG2 to an ON level and turns on the synchronous rectification transistor M200 (timing t11). Accordingly, the drain voltage VDS2 is changed to a voltage value (IS2×Ron) based on an on-resistance of the synchronous rectification transistor M200 and the current IS2.
When the synchronous rectification controller 300S detects that the drain voltage VDS2 has become equal to or higher than a predetermined threshold value Vth at timing t12, the synchronous rectification controller 300S sets the gate signal SG2 to an OFF level and turns off the synchronous rectification transistor M200. Thereafter, the current IS2 flows through the body diode BD until the current IS2 becomes zero at timing t13.
However, a state of the circuit in FIG. 5 described above is an ideal state, and actually, as illustrated in FIG. 6, a parasitic inductor L exists between the drain of the synchronous rectification transistor M200 and a connection node N2 to which the drain terminal Td1 is connected. The parasitic inductor L is generated by a substrate pattern, a bonding wire and lead of the synchronous rectification transistor M200, or the like.
Therefore, the drain voltage VDS2 becomes a value obtained by adding an induced voltage ΔVL generated in the parasitic inductor L to a drain-source voltage ΔVDS of the synchronous rectification transistor M200. The induced voltage ΔVL is ΔVL=L×di/dt.
FIG. 8 is a timing chart illustrating a switching control of the synchronous rectification transistor M200 in the circuit illustrated in FIG. 6. In FIG. 8, the current IS2 flowing through the synchronous rectification transistor M200, the drain-source voltage ΔVDS, the induced voltage ΔVL, the drain voltage VDS2, and the gate signal SG2 are shown sequentially from the top side.
When the switching transistor on the primary side is switched at timing t20 of FIG. 8, the drain-source voltage ΔVDS is changed from a positive voltage to a negative voltage, and the current IS2 starts to flow through the body diode BD. The induced voltage ΔVL, which is a negative voltage, is generated by a temporal slope di/dt of the increasing current IS2. The drain voltage VDS2 is a sum of the drain-source voltage ΔVDS and the induced voltage ΔVL.
When the synchronous rectification controller 300S detects that the drain voltage VDS2 has become a negative voltage, the synchronous rectification controller 300S sets the gate signal SG2 to an ON level and turns on the synchronous rectification transistor M200 (timing t21). Accordingly, the drain-source voltage ΔVDS is changed to a voltage value based on the on-resistance of the synchronous rectification transistor M200 and the current IS2.
The induced voltage ΔVL becomes zero at timing t22 where the current IS2 reaches a peak, and thereafter, the induced voltage ΔVL rises to a positive voltage by a decrease of the current IS2. Accordingly, the drain voltage VDS2, which is a value obtained by adding the induced voltage ΔVL of the positive voltage to the drain-source voltage ΔVDS, becomes equal to or higher than the threshold voltage Vth at timing t23, which is earlier than the timing t12 illustrated in FIG. 7 described above. Thus, at a timing earlier than that in FIG. 7, the gate signal SG2 becomes an OFF level and the synchronous rectification transistor M200 is turned off. Thereafter, the current IS2 flows through the body diode BD until the current IS2 becomes zero at timing t24.
As described above, due to the existence of the parasitic inductor L in the actual LLC converter, there was a problem that the timing when the synchronous rectification transistor M200 is turned off arrives earlier, which results in efficiency reduction. There was also a problem that influence of the parasitic inductor L on the efficiency increases as a load (i.e., the peak of the sinusoidal current IS2) increases.